Thinking of applying? Check your CV against this job first.
See your match score, your strongest skills for this role, and what's missing — before you spend time on an application.
Your real match score
Free CareerPilot account · Takes about 2 minutes
ABOUT THE POSITION
We are looking to hire an ASIC Physical Design Engineer, who is also experienced
reading and writing RTL, to help us design, test and deploy advanced hardware.
As part of our Ultra Low Latency team, you'll have the opportunity to
collaborate with people in areas across the firm, including trading, networking
and research infrastructure.
This isn't a traditional PD role. We're a small team where everyone works across
the chip design process, and we expect our PD engineers to lead with physical
design expertise but think like chip designers. You should be comfortable owning
a PD flow end-to-end, but also able to read and write RTL and reason about
design decisions that cross the front-end/back-end boundary.
If you've spent your career exclusively in PD, this probably isn't the right
fit—but if you've worked across the stack, either because you started as an RTL
designer and moved into PD, or because you were on a smaller team where you had
to wear multiple hats, we'd love to talk.
We're big believers in the ability of tools to improve the productivity,
reliability and day-to-day joy of hardware engineering. That's why we created
Hardcaml, a hardware development toolchain embedded in OCaml. We don't expect
you to know OCaml (we'll teach you here), but we are looking for hardware
engineers who are excited about the advantages that better tools can bring, and
are willing to try new things as a result.
ABOUT YOU
• You have 8+ years hands-on experience building and running modern physical
design flows (e.g., floorplanning, place and route, timing closure, physical
verification, power analysis)
• You don't need to have optimised every last detail of every flow, but you
should have broad enough experience across PD that you can own a flow
end-to-end and know where the risks are
• Beyond PD, you can read and write RTL and understand how front-end design
decisions affect physical implementation—and vice versa; You think about
physical design in the context of the overall chip, not just as a downstream
consumer of a netlist
• You're interested in using software engineering techniques to improve the
hardware design process, and you have experience programming in a high-level
language (Python, C++, Haskell, etc.)
• Fluent in English
If you're a recruiting agency and want to partner with us, please reach out to
agency-partnerships@janestreet.com.